fn1080 rev.3.00 page 1 of 8 apr 2002 fn1080 rev.3.00 apr 2002 CA3162 a/d converters for 3-digit display datasheet features ? dual slope a/d conversion ? multiplexed bcd display ? ultra stable internal ban d gap voltage reference ? capable of reading 99mv below ground with single supply ? differential input ? internal timing - no ex ternal clock required ? choice of low speed (4hz) or high speed (96hz) conversion rate ? hold inhibits conversion but maintains delay ? overrange indication - eee for reading greater than +999mv, - for reading more negative than -99mv when used with ca3161e description the CA3162e and CA3162ae are i 2 l monolithic a/d converters that provide a 3 di git multiplexed bcd output. they are used with the ca3161e bcd-to-seven-segment decoder/driver and a minimum of external parts to imple- ment a complete 3-digit display. the CA3162ae is identical to the CA3162e except for an extended operating tempera- ture range. the ca3161e is described in the display drivers section of this data book. ordering information pinout CA3162 (pdip) top view functional block diagram part number temp. range ( o c) package pkg. no. CA3162e 0 to 70 16 ld pdip e16.3 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 2 1 2 0 nsd msd lsd hold/ zero adj gnd 2 3 v+ gain adj integrating high input low input zero adj 2 2 cap bypass bcd outputs digit select outputs bcd outputs
CA3162 fn1080 rev.3.00 page 2 of 8 apr 2002 control logic counters and multiplex digit drive band gap reference reference current generator hold/ bypass gates osc ? 2048 ? 96 v/i converter threshold det. msd = most sig nificant digit nsd = next significant digit lsd = least significant digit ? gain adj gnd v+ 2 1 2 0 2 2 2 3 high input low input zero adj v+ v+ bcd outputs integrating cap 10 11 8 9 12 1 2 15 16 14 3 4 5 3 4 5 6 7 13 digit select = msd = lsd = nsd conversion control outputs ?
CA3162 fn1080 rev.3.00 page 3 of 8 apr 2002 absolute maximum ratin gs thermal information dc supply voltage (between pins 7 and 14) . . . . . . . . . . . . . . .+7v input voltage (pin 10 or 11 to ground) . . . . . . . . . . . . . . . . . . ? 15v operating conditions temperature range CA3162e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 75 o c thermal resistance (typical, note 1) ? ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 maximum junction temperature. . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s). . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions abov e those indicated in the operational sectio ns of this specification is not implied. note: 1. ? ja is measured with the component mounted on a low effective ther mal conductivity test board in fr ee air. see tech brief tb379 f or details.. electrical s pecifications t a = 25 o c, v+ = 5v, zero pot centered, gain pot = 2.4k ? , unless otherwise specified parameter test conditions min typ max units operating supply voltage range, v+ 4.5 5 5.5 v supply current, i+ 100k ? to v+ on pins 3, 4, 5 - - 17 ma input impedance, z i - 100 - m ? input bias current, i ib pins 10 and 11 - -80 - na unadjusted zero offset v 11 -v 10 = 0v, read decoded output -12 - +12 mv unadjusted gain v 11 -v 10 = 900mv, read decoded output 846 - 954 mv linearity notes 1 and 2 -1 - +1 count conversion rate slow mode pin 6 = open or gnd - 4 - hz fast mode pin 6 = 5v - 96 - hz conversion control voltage (hold mode) at pin 6 0.8 1.2 1.6 v common mode input voltage range, v icr notes 3, 4 -0.2 - +0.2 v bcd sink current at pins 1, 2, 15, 16 v bcd ? 0.5v, at logic zero state 0.4 1.6 - ma digit select sink current at pins 3, 4, 5 v digit select = 4v at logic zero state 1.6 2.5 - ma zero temperature coefficient v i = 0v, zero pot centered - 10 - ? v/ o v gain temperature coefficient v i = 900mv, gain pot = 2.4k ? - 0.005 - %/ o c notes: 1. apply 0v across v 11 to v 10 . adjust zero potentiometer to give 000mv reading. apply 900mv to input and adjust gain potentiometer to give 900mv reading. 2. linearity is measured as a diffe rence from a straight line dr awn through zero and positive full scale. limits do not include ? 0.5 count bit digitizing error. 3. for applications where low input pin 10 is not operated at pi n 7 potential, a return path of not more than 100k ? resistance must be provided for input bias currents. 4. the common mode input voltage above ground cannot exceed +0.2 v if the full input signal range of 999mv is required at pin 11 . that is, pin 11 may not operate higher than 1.2v positive with respect to groun d or 0.2v negative with respect to ground. if the maximum input signal is less than 999mv, the common mode input voltage may be raised accordi ngly.
CA3162 fn1080 rev.3.00 page 4 of 8 apr 2002 timing diagram detailed description the functional block diagram of the CA3162e shows the v/i converter and reference current generator, which is the heart o f the system. the v/i converter converts the input voltage applie d between pins 10 and 11 to a cur rent that charges the integratin g capacitor on pin 12 for a predetermined time interval. at the e nd of the charging interval, the v /i converter is disconnected fro m the integrating capacitor, a nd a band gap reference constant current source of opposite polarity is connected. the number of clock counts that elapse before the charge is restored to its o rig- inal value is a direct measure of the signal induced current. t he restoration is sensed by the comp arator, which in turn latches the counter. the count is then mu ltiplexed to the bcd outputs. the timing for the CA3162e is supplied by a 786hz ring oscillator, and the input at pin 6 determines the sampling rate . a 5v input provides a high speed sampling rate (96hz), and grounding or floating pin 6 provides a low speed (4hz) sampling rate. when pin 6 is fixed at +1. 2v (by placing a 12k resistor between pin 6 and the +5v supply) a hold feature is available . while the CA3162e is in the hold mode, sampling continues at 4hz but the display data are latched to the last reading prior to the application of the 1.2v. removal of the 1.2v restores conti n- uous display changes. note, however, that the sampling rate remains at 4hz. figure 1 shows the timing of sampling and digit select pulses for the high speed mode. note that the basic a/d conversion process requires approxi mately 5ms in both modes. the eee or --- displays indi cate that the range of the syst em has been exceeded in the positive or negative direction, respec - tively. negative voltages to -99mv are displayed with the minus sign in the msd. the bcd code is 1010 for a negative overrange (---) and 1011 for a pos itive overrange (eee). 2ms/div. 200mv 500mv 500mv 500mv pin number 5 (lsd) 4 (msd) 3 (nsd) 12 figure 1. high speed mode figure 2. basic digital readout system using the CA3162e and the ca3161e notes: 1. the capacitor used here must be a low dielectric absorption t ype such as a polyester or polystyrene type. 2. this capacitor should be placed as close as possible to the p ower and ground pins of the ca3161e. ca3161e 10 6 2 1 7 7 13 16 15 1 2 10 k ? 3 8 10 9 15 14 11 12 13 gain adj r1 150 ? r2 150 ? r3 150 ? msd nsd lsd bcd digit inputs high low outputs drivers 4 5 3 16 11 6 normal low speed mode: v6 = ground or open hold: v 6 = 1.2v high speed mode: v 6 = 5v CA3162e 8 12 9 14 0.27 ? f 0.1 ? f note 1 note 2 +5v common anode led displays power 2n2907, 2n3906 or equiv. 1k ? digit driver CA3162e pins 3, 4, 5 75 ? bcd segment drivers CA3162e pins 1, 2, 15, 16 a b c d f g e a b c d f g e a b c d f g e
CA3162 fn1080 rev.3.00 page 5 of 8 apr 2002 CA3162e liquid crystal di splay (lcd) application figure 3 shows the CA3162e in a typical lcd application. lcds may be used in favor of led displays in applications requiring lower power dissipation, such as battery-operated equipment, or when visibility in high-ambient-light conditions is desired. multiplexing of lcd digits is not practical, since lcds must be driven by an ac signal and the average voltage across each segment is zero. three cd4056b liquid-crystal decoder/drivers are therefore used. each cd4056b contains an input latch so that the bcd data for each digit may be latched into the decoder using the inverted digit -select outputs of the CA3162e as strobes. the capacitors on the outputs of inverters g3 and g4 filter out the decode spikes on the msd and nsd signals. the capaci- tors and pull-up resistors connected to the msd, nsd and lsd outputs are there to shorten the digit drive signal thereby pro - viding proper timing fo r the cd4056b latches. inverters g1 and g2 are used as an astable multivibrator to provide the ac drive to the lcd backplane. inverters g3, g4 and g5 are the digit-select inverters and require pull-up resis - tors to interface the open-collector outputs of the CA3162e to cmos logic. the bcd outputs of the CA3162e may be con- nected directly to the corresponding cd4056b inputs (using pull-up resistors). in this arrangement, the cd4056b decodes the negative sign (-) as an l and the positive overload indic a- tor (e) as an h. the circuit as shown in figure 3 using g7, g8 and g9 will decode the negative sign (-) as a negative si gn (-), and the positive overload i ndicator (e) as h. figure 3. typical lcd application +5v to lsd of lcd +5v to msd of lcd +5v to nsd of lcd 1 6 4 2 3 5 78 16 cd4056b 15k ? 100k ? 0.63 ? f to lcd backplane 1 6 4 2 3 5 78 16 cd4056b 1 6 4 2 3 5 78 16 cd4056b 0.047 0.27 ? f zero 50k ? hold v in + gain 10k ? +5v 12 14 8 9 11 10 13 4 3 5 16 15 1 2 7 msd v in - nsd lsd 2 3 2 2 2 1 2 0 ? f 0.047 ? f g1 - g6: cd4049ub hex inverter g7, g8, g9: cd4023b triple 3 input nand gate 0.047 ? f g7 g9 g8 0.047 ? f 0.047 ? f 4 x 100k ? 6 x 10k ? g3 g4 g5 +5v CA3162e
CA3162 fn1080 rev.3.00 page 6 of 8 apr 2002 CA3162e common-cathode, l ed display application figure 4 shows the CA3162e connected to a cd4511b decode/driver to operate a common-cathode led display. unlike the ca3161e, the cd4511b remains blank for all bcd codes greater than nine. after 9 99mv the display blanks rather than displaying eee, a s with the ca3161e. when displaying negative voltage, the first digit remains blank, instead of (-) , and during a negative or positive overrange the display blanks. the additional logic shown within the dotted area of figure 4 restores the negative sign (-), a llowing the display of negativ e numbers as low as -99mv. negative overrange is indicated by a negative sign (-) in the msd position. the rest of the displa y is blanked. during a positive ov errange, only segment b of the msd is displayed. one inverter from the cd4049b is used to operate the decimal points. by connecting the inverter input to either the msd or nsd line either dp1 or dp2 will be dis- played. figure 4. typical common-cathode led application 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 1 / 3 cd4049ub 1 / 3 cd4049ub v+ 1.8k ? 1.8k ? 1.8k ? 1.8k ? 1.8k ? 1.2k ? 1.2k ? 12 11 10 9 8 7 6 5 4 3 2 1 dp1 dp2 fagbc 3 c 1 edc 2 cd p g f v+ e a b c d b c lt bl le/strobe a d gnd 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 v+ c d zero gain int high low b a nsd msd lsd gnd hold zero v+ 0.27 ? f 10k ? gain input v+ 100k ? 100k ? 100k ? 100k ? 50k ? v+ 100 k ? 100 k ? 100 k ? v+ 1 / 6 cd4049ub 1 / 6 cd4049ub cd4012b 22k ? v+ 100k ? dp1 dp2 6 buffers (1 cd4050b) cd4511b CA3162e hp5082-7433 or equivalent
CA3162 fn1080 rev.3.00 page 7 of 8 apr 2002 die characteristics die dimensions: 101 mils x 124 m ils x 20 mils ? 1 mil metallization: type: al thickness: 17.5k ? ? 2.5k ? passivation: type: 3% psg thickness: 13k ? ? 2.5k ? metallization mask layout CA3162 2 1 2 0 nsd msd lsd hold/bypass gnd zero adj zero adj low input high input integrating cap gain adj v+ 2 2 2 3
fn1080 rev.3.00 page 8 of 8 apr 2002 CA3162 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2002. all rights reserved. all trademarks and registered trademarks are the property of their respective owners.
|
